Presently, the existing methods for multiple phase generation can be classified into two broad categories i.e. locking based and calibration based methods. The locking based approach uses a DLL to lock to a phase of 2π through a set of controllable delay buffers. The delay buffers can be controlled by an analog voltage or a digital setting. Since the minimum delay that can be achieved from a buffer is quite coarse, interpolators are used to get resolution less than minimum gate delay. In all these architectures, circuit innovations are done to generate delays with good resolution by keeping the sub-phases as much close to each other as possible. But with increasing process variability, it becomes difficult to maintain the accuracy and resolution at the same time.
FIG. 1 shows a block diagram of a system for generating delays. The delay of the signals tapped at the end of first, second . . . Nth stage with respect to the feedback point (X) is D1, D2, . . . , DN respectively. Due to local mismatch among the delay stages, the delay step added by each stage will vary. To quantify that effect, a simple mathematical model of the system is constructed. The delay of each stage (τi) can be split to have a global component τ0 (constant across all stages) and a local random component δTi. The δTi s are assumed to be independent and identically distributed (i.i.d.) having a Gaussian distribution with zero mean and standard deviation σ[δT].
Hence, the delay of the ith stage can be written as:τi=τ0+δTi  (1)
The delay for the signal tapped after ith stage i.e. Di will now be given by:
                              D          i                =                                            ∑                              k                =                1                            i                        ⁢                          τ              k                                =                                    i              ⁢                                                          ⁢                              τ                0                                      +                                          ∑                                  j                  =                  1                                i                            ⁢                              δ                ⁢                                                                  ⁢                                  T                  j                                                                                        (        2        )            
The delay for the signal tapped after Nth stage is
                              D          N                =                                            ∑                              k                =                1                            N                        ⁢                          τ              k                                =                                    N              ⁢                                                          ⁢                              τ                0                                      +                                          ∑                                  j                  =                  1                                N                            ⁢                              δ                ⁢                                                                  ⁢                                  T                  j                                                                                        (        3        )            
Since the delay at the end of the Nth stage is kept constant by the Phase detector (PD) and Charge pump (CP) to the match input clock period, DN is fixed and τ0 is adjusted by the loop to make
                              τ          0                =                                            D              N                        -                                          ∑                                  j                  =                  1                                N                            ⁢                              δ                ⁢                                                                  ⁢                                  T                  j                                                              N                                    (        4        )            
The variance of the delay at the tapping point is given by:Var[Di]=i*(N−i)/N Var[δT]  (5)
which peaks for i=N/2 and the peak value of the uncertainty in terms of standard deviation is given by
                              Max          ⁢                      {                          σ              ⁡                              [                                  D                  i                                ]                                      }                          =                                            N                        2                    ⁢                      σ            ⁡                          [                              δ                ⁢                                                                  ⁢                T                            ]                                                          (        6        )            
FIG. 2 shows the standard deviation of the generated delays across i for a period (DN) of 5 ns, N=100 and σ[δT]=4 ps. It is found that in conventional DLL based techniques, the delay at the extreme ends of the delay chain are checked using a phase detector. However, if the desired delay is farther from the two ends of the chain, the accuracy degrades as shown in FIG. 2. Therefore, an ideal architecture would use actual generated delay itself in a feedback to ensure accuracy.
Also, the conventional techniques use two PLLs with small frequency offsets to generate precise one-shot delays. But the technique is specifically oriented towards generating one-shot delays proportional to the digital code word and cannot be applied for fractional periodic delay generation. Most of the calibration based approaches use a separate calibration phase to reduce the error. Therefore, they can't be adopted for applications requiring uninterrupted signal to be available for a long time. Moreover, with slow temperature variations, the delays generated by these calibration based systems can change causing an increase in error. Some calibration based approaches generate a physical signal to calibrate the generated delayed signal against a reference. For example, in one of the known technique a high resolution TDC within a FPGA using dynamic reconfiguration where a variable frequency oscillator is used for the calibration to ensure the accuracy of the intermediate step delays against temperature variation and mismatch. In the calibration phase, the variable frequency generator is used to generate the reference signal whose phase is compared with each of the delay elements to find the nearest delay stage for a required delay. The frequency of the variable frequency oscillator drifts with time due to increase in temperature making re-calibration necessary at regular intervals when the system needs to be put on hold. The hardware required and time required for calibration process is also relatively high.
Further, another conventional technique uses a high resolution digital to time converter where an integrated Dual Mixer Time Domain (DMTD) circuit is adopted to overcome device mismatch, process variations and temperature for self-calibration during normal operation. Similarly, an on-chip measurement and continuous correction methods for correcting output duty cycle where random sampling technique is used for delay estimation. However, no experiment result is demonstrated for the aforementioned techniques to reveal the actual performance of the PDG. Also, these techniques use a conventional XOR based approach which can give an erroneous estimate for skews around zero in the presence of jitter.
A technique to provide solution to all these problems, and to enable a continuous closed loop feedback ensuring good accuracy in achieving a desired fractional period delay with little area overhead is required.